This project makes use of one of my earlier designs, the Quadrature Encoder in VHDL (but targeted to for the Altera Cyclone-II on the DE2-70 board). The basic idea behind this design is to control the Quadrature Encoder output rate based on user input via the CapSense inputs. As an overview, the top-level schematic is shown below.

The design is very simple. The DivisorGenerator module accepts 3 CapSense inputs and generates a bounded divisor output that feeds the QuadratureEncSM module. The CapSense inputs are defined such that PUSH_A decreases the output frequency. PUSH_B increases the output frequency and PUSH_C controls the frequency change steps (either by 10 or by 1 when PUSH_A or PUSH_B are pressed), in other words, a fine tune selector. Further, the current fine tune setting is reflected by LED2 (C16). If LED2 is ON then the frequency changes will be in steps of 10, otherwise they will be in steps of 1. The QuadratureEncSM module outputs to various pins on the J4 connector (A=A13, B=A14, Z=C13). Finally, there is a FrequencyDivider module that serves to output to LED1 (D14) to show that the design is running (heartbeat).

The good thing about this board is that it can be programmed via USB using the utility supplied by Avnet. Furthermore, if desired, the board can be driven by USB power only, thus doing away with any external power source. I programmed the bitstream in SPI flash, therefore, the design comes up on power-up.

The project archive can be downloaded below.

Popularity: 5% [?]

This is a step-by-step guide on my first project on the Avnet Spartan-3A. This will be a very simple project concentrating on the tool flow as opposed to design. To keep things simple we will capture the top level design as a schematic. The design will consist of blinking LED1 (pin D14) at a given rate and controlling LED2 (pin C16) via the CapSense input PUSH_A (pin K3).

The steps to get this going can be summarized as follows:

1. New Project: Start ISE and setup a new project
2. Add sources: Convert all VHDL modules into schematic symbols and then capture the top-level design via schematic capture in ISE.
3. Map I/O: Map inputs and outputs to pins
4. Compile: Compile the design
5. Simulate: Simulate and correct as needed
6. Program Device: Create the bitstream and load into device.

1. New Project

Start the new project wizard by selecting “File—>New Project…” (note that I will be using the latest WebPack version of ISE—version 11). Select a name for the project, a location and optionally give a description. Finally, select the top-Level source type to “Schematic” from the drop-down. See below.

In the next window select device properties. On the Avnet evaluation board we have the 256 pin, Spartan-3A XC3S-400A, speed grade 4 (refer to the Spartan-3A datasheet for details). The following is an excerpt of the package markings

The final settings on the device properties window should be as follows:

Ignore the “Create New Source” window by clicking Next. Do the same for the “Add Existing Sources” window. The last window shows the project summary, click Finish to continue. At this point ISE should look as shown below

2. Add Sources

Create the top-level schematic file by right-clicking on “xc3s400a-4ft256” and selecting “New Source …”. The New Source Wizard will start up. Now select “Schematic” from the selections given, set a file name and hit Next. As follows,

A summary page appears, click Finish to continue. ISE will now automatically open the schematic capture tool as follows:

Now before we continue to schematic capture we need to add a frequency divider module to our design files that will allow us to scale down the FPGA input clock to a smaller value so that it is visible when output to LED1. To do this we will now add a VHDL source to our design. To move away from schematic capture select the “Design” tab from the list of tabs shown in the “Symbols” pane (tabs shown are Design, Files, Libraries and Symbols (currently selected)). After the selection the “Symbols” tab becomes the “Design” tab as follows:

Now as before right-click on “xc3s400a-4ft256” and select “New Source …”, then select “VHDL Module” as the new source and give it a file name, as follows,

Click Next to continue. This will bring up the “Define Module” window of the Wizard. Here set the inputs and outputs of the module as follows (clkIn=IN, divisor=IN(31..0), clkOut=INOUT):

Click Next and then Finish to continue. ISE now shows the basic VHDL module as follows:

We now need to fill in the main code into the VHDL file. Copy and paste the following code into the architecture definition.

PROCESS(clkIn)
    VARIABLE count : STD_LOGIC_VECTOR(30 DOWNTO 0);
    VARIABLE clkOut_t : STD_LOGIC;
BEGIN
    IF(clkIn’EVENT AND (clkIn = ‘1′)) THEN
        count := count + 1;
        IF(count = divisor(31 DOWNTO 1)) THEN
            clkOut <= NOT clkOut;
            count := (OTHERS => ‘0′);
        END IF;
    END IF;
END PROCESS;

The ISE code editor window should look as follows:

Now save the file (CTRL-S) and select “FrequencyDivider” from the file list in the design hierarchy pane. Doing this changes the pane below the Design pane to show the design utilities for the selected file, as follows:

Now double click “Create Schematic Symbol” (highlighted in yellow) to create a schematic symbol of the FrequencyDivider module. Once this process is over double-click on “FirstProject” in the xc3s400a-4ft256 hierarchy (circled in red above). This will now bring up the schematic capture editor. Now the “Design” pane is replaced by the “Symbols” pane. Here all the available symbols are shown including the newly created “FrequencyDivider” symbol. It is possible that this symbol is not shown in the list since the list is not updated. I found that right-clicking in the schematic editor to bring up the context menu has the effect of updating the schematic table, as follows:

Now drag and drop the various modules needed to create our design. This includes the FrequencyDivider, a “constant” under the “General” category and ibuf and obuf under the “IO” category, as follows

Now select the “Add Wire” tool shown in the red circle and connect the ports. Hit ESC to get back to selection mode and double-click on “constant”. This will bring up the “Object Properties” window where the “CValue” needs to be changed to 0×00FFFFFF. Hit OK to continue, as follows:

The Schematic editor should now look as follows:

3. Map IO

We now need to add IO markers or pads. To do this select the “Add—>I/O Marker” menu item (or simply hit CTRL-G) and click on all the IO points in the design. This schematic will now look as follows:

Now assign sensible names to these markers by double-clicking on the IO markers. For example double-clicking the clkIn marker into FrequencyDivider module brings up the following “Object Properties” window. Select the yellow highlighted marks and rename the port. Note the PortPolarity for the port (circled in red). Do the same for the rest. However, for the output port (clkOut) of FrequencyDivider select the PortPolarity from “Bidirectional” to “Output”.

The final schematic is shown below:

Save by hitting CTRL-S or from the menu “File—>Save”. Now select the “Design” tab and select the top-level module FirstProject under the xc3s400a-4ft256 hierarchy. This will bring up various items in the “Processes” pane below the “Design” pane. Now expand the “User Constraints” menu item and double-click on the “I/O Pin Planning (PlanAhead) – PreSynthesis” item, shown highlighted in yellow below:

Since no User Constraints file was created we will be asked to create one, as follows:

Select “Yes” to continue. This will open the “PlanAhead” tool as a separate window.

Now select the various ports under the “I/O Ports” pane (highlighted in yellow) and drag and drop the pins into the pin window (red arrow). The mappings are: clk=>C10, LED1=>D14, LED2=>C16, PUSH_A=>K3. The “I/O Ports” pane should now look as shown below:

Now exit PlanAhead. Now the “Design” tab in ISE should have a file called FirstProject.ucf, right-click on this and select “Open”. This should bring up the “Timing Constraints” pane and editor as shown below:

Now double-click on the editor (highlighted in yellow) to add the clock timing constraints. This will bring up the “Clock Period” window where the clock period for the board can be entered (note that on certain occasions I find that on Vista the tool fails to open with some error pertaining to “TEMP” folder not defined. I simply ignore this error and retry and this usually works OK) . This is 16MHz clock so add 62.5ns in the “Time” textbox, highlighted in yellow, below:

Hit OK to continue. Now save this file by hitting CTRL-S.

4. Compile

Now select the “Design” tab to go back to the design processes. Here select “FirstProject” under the xc3s400a-4ft256 hierarchy and then double-click on “Implement Design” to synthesize and implement the design, as follows (highlighted in yellow):

5. Simulate

I will skip this step for this simple project and take it up in a future posting.

6. Program Device

Now select “Generate Programming File” from the Processes menu to generate the programming file. If you have enabled “WebTalk” then the appropriate “WebTalk” dialog shows up, so respond as needed. Now we will open the Avnet tool AvProg to download the file. Select the highlighted options to connect to the Serial Port, then browse to the Bit File (firstproject.bit) and finally Configure the FPGA, as follows:

The final screenshot of AvProg is shown below. Note the highlighted message indicating that the FPGA programmed successfully.

You will now notice that the LED1 is blinking and that touching the CapSense input PUSH_A causes LED2 to change states.

Notes:

1. I found that the latest edition of ISE WebPack v11 is more stable then v10. I was endlessly fighting the tool when I was using v10 which spuriously kept on changing the UCF file associated with the top-level file—very frustrating.
2. On Vista, I occasionally get a “TEMP” folder does not exist error during various processes (synthesis, UCF creation, etc). I have found that repeating the step normally resolves this problem.
3. When a new file is added to an empty project then the added file is automatically marked as the top-level file. If more files are added later then the top-level file can be reassigned to a new file by simply right-clicking on the file and selecting “Set as Top Module” from the menu. As an example if, in Step 2 above, the VHDL module (FrequencyDivider) was added before the schematic FirstProject then FrequencyDivider would have been marked as the top-level module and subsequent steps would fail. Therefore, we would have to mark the FirstProject file as the top-module before progressing to other steps.

The ISE project archive is included below for download.

Popularity: 8% [?]

I have to apologize to anyone following this blog since it has been a while since I posted any content. I hope to have new content soon. There are several projects that I have been working on ranging from FPGA related stuff to general tools support for my work. I find that in the Embedded world visualization is seriously lacking and to that end I have some ideas that I have been working on, more on this later. In the meantime, I find Microsoft’s new WPF technology to be amazing compared to their previous generation WinForms framework for GUI building and general visualization. I have been bringing myself up to speed on this amazing technology and find it a lot of fun to work with. I hope to have some posts or tools using that technology in the near future. In the meantime, thanks for visiting my blog.

Popularity: 2% [?]

In this post I will outline a couple of solutions for a quadrature encoder generator in VHDL. I wanted a Quadrature Encoder signal for test purposes without the need to hook-up a real encoder and decided that an FPGA is perfect for this, especially considering that generating two signals with a 90-degree phase shift is not easy using analog means.

The basic specification for this task can be summarized as follows:

Inputs:

• System clock: I will use the 50MHz clock iCLK_50 on the DE2-70
• Reset.
• Divisor: Divides the system clock to achieve a desired quadrature encoder output frequency.
• Direction: Defines the rotational direction of the quadrature encoder
• PPR: Pulses Per Revolution. A quadrature encoder characteristic. Encoders can be purchased with different PPR settings. A Z pulse is generated every this many A or B pulses.

Outputs:

• A: Quadrature Encoder Output. 50% duty cycle.
• B: Quadrature Encoder Output. 50% duty cycle. 90-degree phase shifted off A. Phase shift plus or minus depends on direction of travel.
• Z: Reference pulse generated every time the encoder completes 1 revolution (as given by PPR). The pulse width is equal to half the width of an A/B pulse.

Quadrature Encoder in VHDL Solution 1

This basic solution consists of 2 processes. The first process generates the A/B pulses while the second process generates the Z pulse.

The First Process

This process is divided into two parts (although this may not be obvious in the implementation). The first part simply generates a temporary 50% duty cycle base signal (representing the signal A or B) using the Divisor input to generate the given output frequency based off the system clock. The 90-degree phase shifted second temporary signal is based off this first base signal and is generated by counting half the number of Divisor system clock cycles every time the base signal transitions. Once this count is reached the output (second signal) takes on the value of the base signal. Finally, the Direction parameter decides how these temporary signals are assigned to the outputs A and B. The following diagram illustrates this.

Quadrature Encoder Solution 1

Notes:

• The divisor input parameter above is used to toggle the output every time that many system clock pulses are counted. In other words, the output pulse width of the A/B quadrature encoder pulse is 2 times the Divisor number of system clock pulses. This means that we can only generate the output frequency in multiples of 2. In summary, the output quadrature encoder frequency is given by
  

The Second Process

This process is very simple. It clocks off the A pulses generated by the first process and counts PPR number of transitions. A Z pulse is then generated when the count is reached. It then resets and repeats.

The Solution

-- Quadrature Encoder
-- Author : Hitesh Patel, November 2008
--          blog.nirosoftware.com
--
LIBRARY ieee;
 
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
 
ENTITY QuadratureEnc IS
	GENERIC (NumBits : INTEGER := 26;
	PPR : INTEGER := 4);-- Pulses Per Revolution. Z generated every PPR count
	PORT( clk, rst : IN STD_LOGIC;
	      divisor : IN STD_LOGIC_VECTOR(NumBits-1 DOWNTO 0); -- 26 bits, must be multiple of 2
	      direction : IN STD_LOGIC; -- '1' => CLOCKWISE; '0' => ANTI-CLOCKWISE
	      A : BUFFER STD_LOGIC;
	      B : OUT STD_LOGIC;
	      Z : BUFFER STD_LOGIC);
END QuadratureEnc;
 
ARCHITECTURE QuadratureEnc OF QuadratureEnc IS
		SIGNAL clkCountB : STD_LOGIC_VECTOR(NumBits-1 DOWNTO 0);
		SIGNAL div : STD_LOGIC_VECTOR(NumBits-1 DOWNTO 0);
BEGIN
	-- Make divisor a multiple of 2 otherwise incorrect signal patterns
	-- are generated
	div(0) <= '0';
	div(NumBits-1 DOWNTO 1) <= divisor(NumBits-1 DOWNTO 1);
	PROCESS(clk, rst)
		VARIABLE clkCountA : STD_LOGIC_VECTOR(NumBits-1 DOWNTO 0);
		VARIABLE startCount : BOOLEAN;
		VARIABLE signalA, signalB : STD_LOGIC;
	BEGIN
		IF(rst = '1') THEN
			clkCountA := (OTHERS => '0');
			clkCountB <= (OTHERS => '0');
			signalA := '0';
			startCount := False;
		ELSIF (clk'EVENT AND clk='1') THEN
			clkCountA := clkCountA + 1;
			IF(clkCountA = div) THEN
				clkCountA := (OTHERS => '0');
				signalA := NOT signalA;
				startCount := True;
			END IF;
			IF(startCount) THEN
				clkCountB <= clkCountB + 1;
				IF(clkCountB = To_StdLogicVector(To_bitvector(div) SRL 1)) THEN
					clkCountB <= (OTHERS => '0');
					signalB := signalA;
					startCount := False;
				END IF;
			END IF;
		END IF;
		IF(direction = '1') THEN -- CLOCKWISE
			A <= signalB;
			B <= signalA;
		ELSE -- ANTI-CLOCKWISE
			A <= signalA;
			B <= signalB;
		END IF;
	END PROCESS;
 
	-- Process that generates the Z reference pulse
	PROCESS(A, clk)
		VARIABLE countA : STD_LOGIC_VECTOR(NumBits-1 DOWNTO 0);
	BEGIN
		IF (A'EVENT AND A='1') THEN
			Z <= '0';
			countA := countA + 1;
			IF(countA = PPR) THEN
				Z <= '1';
			END IF;
		END IF;
	END PROCESS;
 
END QuadratureEnc;

Download the project below

Quadrature Encoder in VHDL Solution 2

This design came to me in a moment of inspiration while I was perusing some quadrature encoder data sheets! Anyway, this design uses a state machine to generate the output. Note how A and B change in the diagram below as the encoder rotates in a given direction.

Quadrature Encoder Signals A/B

The repeating pattern can be captured in a state machine which transitions every N (or Divisor) system clock cycles, as shown below.

Quadrature Encoder State Machine, Clockwise Rotation

Quadrature Encoder State Machine, Counter Clockwise Rotation

This implementation uses a classic state machine design pattern consisting of 2 processes. The first process consists of sequential logic and is responsible for state transitions. In this case the state transitions are predicated by a counter. This is the same counting logic as in design 1 above to generate a given Quadrature Encoder frequency. The second process is responsible for signal assignments and assigning the next state. I have left out the logic that generates the Z pulse to keep the implementation uncluttered for purposes of illustrating the simplicity of the design.

The Solution

-- State Machine based Quadrature Encoder
-- Author : Hitesh Patel, December 2008
--          blog.nirosoftware.com
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
USE ieee.std_logic_unsigned.all;
 
ENTITY QuadratureEncSM IS
	GENERIC (NumBits : INTEGER := 26;
	PPR : INTEGER := 4);-- Pulses Per Revolution. Z generated every PPR count
	PORT( clk, rst : IN STD_LOGIC;
	      divisor : IN STD_LOGIC_VECTOR(NumBits-1 DOWNTO 0); -- 26 bits, must be multiple of 2
	      direction : IN STD_LOGIC; -- '1' => CLOCKWISE; '0' => ANTI-CLOCKWISE
	      A : OUT STD_LOGIC;
	      B : OUT STD_LOGIC;
	      Z : OUT STD_LOGIC);
END QuadratureEncSM;
 
ARCHITECTURE QuadratureEncSM OF QuadratureEncSM IS
		TYPE state IS (s00, s01, s11, s10);
		SIGNAL pState, nState : state;
		SIGNAL aa, bb, zz : STD_LOGIC;
BEGIN
	-- State machine control
	PROCESS(clk, rst)
		VARIABLE clkCountA : STD_LOGIC_VECTOR(NumBits-1 DOWNTO 0);
	BEGIN
		IF(rst = '1') THEN
			pState <= s00;
			clkCountA := (OTHERS => '0');
		ELSIF (clk'EVENT AND clk='1') THEN
			clkCountA := clkCountA + 1;
			IF(clkCountA = divisor) THEN
				clkCountA := (OTHERS => '0');
				pState <= nState;
			END IF;
			-- Output signals
			A <= aa;
			B <= bb;
			Z <= zz;
		END IF;
	END PROCESS;
 
	-- Quadrature Encoder state machine
	PROCESS(pState, rst)
	BEGIN
		IF(direction = '1') THEN -- clockwise
			CASE pState IS
				WHEN s00 =>
					nState <= s01;
					aa <= '0';
					bb <= '1';
				WHEN s01 =>
					nState <= s11;
					aa <= '1';
					bb <= '1';
				WHEN s11 =>
					nState <= s10;
					aa <= '1';
					bb <= '0';
				WHEN s10 =>
					nState <= s00;
					aa <= '0';
					bb <= '0';
			END CASE;
		ELSE -- Counter clockwise
			CASE pState IS
				WHEN s00 =>
					nState <= s10;
					aa <= '1';
					bb <= '0';
				WHEN s10 =>
					nState <= s11;
					aa <= '1';
					bb <= '1';
				WHEN s11 =>
					nState <= s01;
					aa <= '0';
					bb <= '1';
				WHEN s01 =>
					nState <= s00;
					aa <= '0';
					bb <= '0';
			END CASE;
		END IF;
		zz <= '0';
	END PROCESS;
END QuadratureEncSM;

In conclusion this design methodology lends itself very well to generating interesting repeating output patterns. One simply maps out the desired pattern for the output signals and captures this in a state machine.

Download the project archive below

Popularity: 49% [?]

OK here is a bit of digression from the usual programming. Anyone who has had the misfortune of losing data knows only too well that a reliable backup scheme is very important. However, reliability is just one of the important criteria. Another, IMHO, is ease of use or more to the point minimal intervention to keep the backup running stably. I have gone through many cycles of downloading and using many backup tools (paid or otherwise). There was always some problem right down from configuring the tool to backups failing outright for simple things such as locked (or in-use) files. When one gets busy this kind of manual intervention is precisely the kind of thing that gets neglected and then bam! before you know it you need to recover some important data. The title of this post refers to CrashPlan. CrashPlan is one hell of a backup solution meeting all the criteria I had been seeking. However, until recently CrashPlan could only backup up to a remote machine be it their storage server (per GB cost) or your friend’s/family member’s remote machine (FREE). There was only one thing missing for me to qualify it as a top backup software and that was backup to local storage. This just changed in the latest version of CrashPlan and now, as far as I am concerned, this makes CrashPlan one of the best backup software out there. I am not in any way paid to write anything I am currently penning. I just wanted to share because I had looked high and low before discovering CrashPlan and it is worth every penny. If you are a programmer or someone interested in document versioning then
the continuous incremental backups feature of CrashPlan (only available in the “+” version of CrashPlan—CrashPlan+) alone is worth the price of the software. I believe that this feature of CrashPlan is an excellent compliment to a version management scheme (CVS, Subversion, SourceSafe, whatever). Here is your typical programmer scenario. You code like crazy, but wait for a check-in until you have reached some mini milestone. However, you end up introducing some subtle bug since the last test you did (mind you you may not have checked-in after every test, there may have been many small tests since you last checked-in). What now? If only you could see the changes you introduced that broke the code. Perhaps you need to rollback to day before yesterday’s code or perhaps yesterday’s code. The incremental continuous backup feature of CrashPlan has saved me hours looking for those subtle changes that may have triggered meltdown. So there, if you are a programmer or, for that matter, anyone who needs document versioning you cannot go wrong with CrashPlan. I also use it to backup all my family data (photos, etc). Finally, for the paranoid security types out there CrashPlan encrypts and compresses all data BEFORE it leaves your machine to it’s desired destination be it your friends machine or to any external server so that you can rest assured that your data is for-your-eyes-only no matter where it is. Seriously, do yourself a favor look into CrashPlan if you are considering a backup solution, personal or otherwise.

Popularity: 8% [?]

I recently acquired a Xilinx Spartan-3A development Evaluation Board for a mere US $39.00. Yes believe it. It is reasonably feature rich and comes with a MicroBlaze demo application installed. I have just started work with it and plan to release some projects in the near future. I believe it is excellent for a beginner. It also has an online forum dedicated to it. The start-up tutorial (entitled “ISE FPGA Design Introduction”) that can be downloaded from the board web page is also excellent.

The Avnet Xilinx Spartan 3A Evaluation Board

Popularity: 100% [?]

In a couple of previous posts (Counter and Seven Segment Display Decoder) I had put together components designed earlier (a simple counter and a seven segment decoder) for the sake of testing out the components, in particular the seven segment decoder. In that test the top-level entity was constructed entirely in Quartus II via schematic capture. In schematic capture the connection of individual VHDL entities is very easy and the visual nature of the scheme means that one can get a very quick overview of the designer’s intent. However, this hides the details of how the components connect in VHDL and, further, makes the design less portable since the schematic format is proprietary to Altera. I wanted to get a better handle on this and, therefore, decided to implement the same test entirely in VHDL. This, hopefully, gives a better feel for how hierarchical (software equivalent: top-down) design is achieved. I also think that it is important to get into hierarchical or block design early on so that one can start abstracting designs from the beginning.

I will not repeat the intent of the design and refer the reader to this previous post Seven Segment Display Decoder Test (the schematic is clear on what is intended). In summary, count KEY0 presses and display on the seven segment HEX0. This consists of a counter, a seven segment decoder and the top-level entity that combines these other entities. The code below show only the top-level entity. Notice how the counter and the seven segment decoder entities are instantiated via the COMPONENT declaration. Further, note how the signals are mapped via the PORT MAP construct. Also notice how the output of counter is input into the seven segment decoder via a signal.

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-- Seven Segment Display Test. All code is VHDL ONLY.
-- In this project I wanted to attempt the same thing as in in the previous project where
-- where I tested the seven segment display driver. However, in the previous project the 
-- top-level entity was created via schematic capture while here I want to do the same but
-- entirely in VHDL. 
-- Author: Hitesh Patel, November 2008
--         blog.nirosoftware.com
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
ENTITY SSDDriverLogic_TestVHDL IS
    -- NOTE: the following port names are mapped to actual pins. Open the Pin Planner for details.
	PORT( iKEY : IN BIT_VECTOR(3 DOWNTO 0); -- We will clock our design with the iKEY[0]
	      oHEX0_D : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); -- we will output the counter data
												      -- to the seven segment HEX0
	      oHEX0_DP : OUT STD_ULOGIC); 
 
END SSDDriverLogic_TestVHDL;
 
ARCHITECTURE SSDDriverLogic_TestVHDL OF SSDDriverLogic_TestVHDL IS
	--------------------
	COMPONENT counter IS
		GENERIC (NumBits : INTEGER := 4);
		PORT ( clk, clr : IN BIT;
			   c : OUT STD_LOGIC_VECTOR (NumBits-1 DOWNTO 0));
	END COMPONENT counter;
	--------------------
	COMPONENT SevenSegmentDisplayDriver IS
		PORT ( d : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
			   dp : IN STD_LOGIC;
			   s : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
	END COMPONENT SevenSegmentDisplayDriver;	
	--------------------
	SIGNAL cnt : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
	counter1: counter PORT MAP(clk=>iKEY(0), clr=>'0', c=>cnt);
	ssd: SevenSegmentDisplayDriver PORT MAP(d=>cnt, dp=>'1', s(6 DOWNTO 0)=>oHEX0_D, s(7)=>oHEX0_DP);
END SSDDriverLogic_TestVHDL;

This code brings out all the elements of a typical design and an analogy to software development (especially from the view point of C code) can help better gel the ideas, particularly if you come from that background. In that light note the following:

• The top-level design entity is equivalent to main() in C
• The individual entities are equivalent to function definitions in C
• The COMPONENT declarations in the top-level design entity’s ARCHITECTURE block is equivalent to a function declaration in C.

This analogy can be extended further if we look at creating libraries of common entities. However, I will elaborate on this later since I do not use that in the example presented here.

Popularity: 16% [?]

I recently had a need to brush up on some analogue electronics and discovered, to my surprise, that there are some excellent free tools to help one learn and probably avoid some expensive mistakes before building actual circuits. Most of these tools are based on the famous SPICE simulation engine originally developed at University of California, Berkeley. Anyway, I wanted to share my discovery with anyone who may be in the same position as me and in want of some help. There are various commercial and free SPICE tools out there. I found that using the free with no-time-limit evaluation versions of commercial tools is a better bet than the free versions since these tools tend to be updated more often. One drawback with this is that vendors who offer the free to use no-time-limit evaluation versions of their tools tend to limit them in some way (obviously). However, for most small circuits they are an excellent alternative to nothing or dated free tools. One trick that may be handy when using these neutered versions of tools, for large circuits that break the limitations of the simulators, is to simulate the large circuit as mini sub-circuits. Once the behavior of the sub-circuit is determined one can replace the sub-circuit with a component (passive or active) for a particular condition one is trying to look at. It can get cumbersome but can help when no other avenues exist. However, this may not always be possible but I have found some use in doing so. It has also improved by intuition in circuit design since one starts looking at circuits as blocks and approximating their behavior for basic quick analysis.

Two simulators that I played with are 5Spice and SIMetrix/SIMPLIS Intro version. The former is page limited (see their FAQ entry for details on limitations and use restrictions) and the latter is node/parts limited, see here for details. Like all tools there is the obvious learning curve since each tool may do things differently, however, the pay-offs are worth the effort. Finally, if you are a student the one tool that you cannot go wrong with is the National Instruments student edition of MultiSim. I have been playing with the evaluation version of the tool and for $39.95 (student pricing, proof required) it is worth every penny and then some. Unfortunately, the base Pro version of Multisim is substantially more expensive (~$1500). Keep in mind that all these tools will simulate mixed mode circuits, that is, both digital and analogue circuits combined.

If commercial tools are not your thing then XSPICE by Georgia Tech may be worth looking into. It is public domain and based on the latest SPICE3. As far as I can tell, unfortunately (or fortunately!), it is provided as source and runs on Unix/Linux systems only. Spice OPUS is another that may be worth looking at, it is based off XSPICE with further optimizations added. Both these appear to be quite dated.

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In this post I will hook-up the input of the Seven Segment Display logic to an up-counter that is clocked by KEY0. The output of the Seven Segment Display logic will drive the HEX0 segment on the DE2-70. This basic test will confirm the working of the Seven Segment Display logic constructed in the previous post. Note that as of this project onwards I will now use the full pin assignment imported into the project via the CSV file furnished by Terasic (import through Assignments–>Import Assignments…).

The top-level schematic for this test appears as shown below. This is basically a hook-up of logic blocks (in this case a counter and a seven segment driver) constructed in earlier posts.

Seven Segment Driver Test

The Quartus II project archive file is attached at the end of this post for download.

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We need a basic user interface component to display current settings, such as the current frequency of a frequency generator, say. To this end I will use the seven segment display (SSD) present on the DE2-70. Here I present two designs. One is a straight up look-up table and the other uses a minimized logic function (minimized via Karnaugh Maps) to drive the segments. Note that for the DE2-70 the output logic for driving segments is negative. Thus to turn ON a segment you write a ‘0′ and to turn OFF a segment you write a ‘1′.

Simple Seven Segment Display Driver

The following truth table captures the output for all possible inputs. Note that I plan to display data in hexadecimal and, hence, I am capturing all inputs. The truth table can simplified in the case where one is only displaying digits (0-9) since don’t cares will appear allowing better minimization. Also note that here I am capturing the output as it should be, meaning 0 turns the segment ON and 1 turns the segment OFF. Finally, keep in mind that on the DE2-70 segment a is connected to HEX?_D[0], segment b to HEX?_D[1], etc

…click here to read more

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