I will not go into the details of how SignalTap II (.stp) files are created and added to a design as these steps are fully detailed in the online tutorial # OCDSW1165. Before we begin, however, we need to add a clock to our design as SignalTap needs a clock to use for capturing. If we were to continue without this step we would find that when we come to selecting the clock setting that we have no clock and would need to backtrack before we can progress. We will preempt such a failure by adding the signal to our design before we go on. We will assign pin PIN_R3 which is a 50MHz input clock to the chip and add this to our schematic. I will not detail these steps here since we have covered these previously. The final schematic is shown here.

We will add KEY0 and LEDG0 as our signals to capture and use for trigger conditions.

Notice that we can see our input pin KEY0 but the output pin is not available. This is because output pins cannot be directly captured, we need to capture the signal driving the output pin. However, since we are using the post-fit filter (as detailed in tutorial OCDSW1165) we do not see the corresponding driving signal. To do this we need to open the RTL viewer and note that we want inst since this is the signal driving the output.

We now select our two signals iKEY0 and inst. However, before progressing any further note that a dialog appears that warns whether we want to set the “netlist type of the Top partition to Post-Fit since you are adding post-fitting nodes?” as shown here. You must select NO if you are using the free Web version of the tools, otherwise you will encounter incremental-compilation errors.

Once the signals have been added we will set up as shown here. We will trigger on the rising edge of KEY0 and remove inst from the trigger list. We will capture data from both these signals. The final SignalTap II configuration is shown here.

Note that we have selected CLK1 for our sampling clock and we have opted for a segmented capture of up to 4 triggers. This will allow us to capture 4 rising edge transitions. Once selected re-compile the design. We will now download the design through the SignalTap II interface. The tutorial mentioned earlier in this post gives details about this. Once loaded the logic analyzer needs to be armed before we can acquired data. Arm SignalTap and hit KEY0 a few times to see what happens.

Notice that we had to hit KEY0 4 times before SignalTap II stop acquisition and displayed the data. We could have gone with a single trigger but this segmented trigger helped us to determine an important thing: that it is safe to assume that we do not need to debounce KEY0 (note that all the KEY inputs go through some conditioning via the 74HC245 buffer chip, which is not a debouncer). If KEY0 bounced then on a single KEY0 hit we would have multiple transitions causing the logic analyzer to trip sooner.

Here is the earlier project including SignalTap II.

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