Now that we have a handle on the basic design flow we need to start working with VHDL to get on to bigger projects. Again to get a handle on working with VHDL I decided that I will take our original first project and capture it entirely in VHDL. It may be prudent to look at the following online course OHDL1110.

I have added two Quartus II project archive files at the end of this post. The first one (example 1) is my naive rendition of the original design. The second one (example 2) makes direct use of the T-flip-flop from the Altera library. Before you progress, I suggest that these projects be loaded and compiled (and simulated). The following summarizes what I think are key points to take away from this exercise.

Example 1

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-- Toggles LEDG0 on KEY0 press
-- Author: Hitesh Patel, 2008
--         blog.nirosoftware.com
 
ENTITY MyFirstProjectVHDL IS
	PORT(	clk : IN BIT; -- This is really KEY0
			q : OUT BIT;  -- This is LEDG0
			clk1 : IN BIT); -- This is 50MHz CLK1 for SignalTap II
END MyFirstProjectVHDL;
 
ARCHITECTURE MyFirstProjectVHDL OF MyFirstProjectVHDL IS
BEGIN
	PROCESS (clk)
		VARIABLE t : BIT;
	BEGIN
		IF(clk'EVENT AND clk='1') THEN -- riding edge occurred
			t := NOT t;
			q <= t;
		END IF;
	END PROCESS;
END MyFirstProjectVHDL;

In this example notice the following:

1. The VHDL entity must have the same name as the top-level entity shown in the project hierarchy, otherwise you will get the “top level design entity undefined” error during compile.
2. The device pins that will map to the entity are assigned the same names as port declarations. As shown here. This was a missing link in my understanding at this VHDL level.


Pin Planner

3. The design in not a classic T-flip-flop it is simply toggling (LEDG0) on every positive transition of the clock (KEY0). Notice also that the initial value of our temporary t is undefined, so we do not know what it will start as. I do not have a deep enough understanding to comment on this yet, but my software spider-sense is tingling.
4. Finally, we have a spare input clk1 needed as a sampling clock for use in SignalTap. I do not know of another way to make it available, this appears to work fine.

Compile the design, simulate and then download and run on the device. It may be prudent to look at the design in the RTL viewer to see what was synthesized, this may help answer our earlier question of what the initial state of t is.

RTL Viewer, Example 1

Example 2

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-- 
-- First VHDL project, example 2, Target Altera DE2-70. 
-- Toggles LEDG0 on KEY0 press
-- Author: Hitesh Patel, 2008
--         blog.nirosoftware.com
 
LIBRARY ieee;
USE ieee.std_logic_1164.all; -- for STD_LOGIC
LIBRARY altera;
USE altera.maxplus2.all; -- we will use the t flip-flop (tff)
 
ENTITY MyFirstProjectVHDL IS
	PORT (	iKEY0 : IN STD_LOGIC;
			oLEDG0 : OUT STD_LOGIC;
			CLK1 : IN STD_LOGIC
		);
END MyFirstProjectVHDL;
 
ARCHITECTURE MyFirstProjectVHDL OF MyFirstProjectVHDL IS
	-- We are going to create an instance of a T flip-flop and use that
	-- in our design
	SIGNAL one : STD_LOGIC;
BEGIN
	one <= '1';
	tff1: TFF PORT MAP(clk=>iKEY0, q=>oLEDG0, t=>one, clrn=>one, prn=>one);
END MyFirstProjectVHDL;

In this example I did the same thing as the last project except that I used the Altera library to instantiate a T flip-flop. Note the following about this example:

1. The top-level VHDL entity instantiates the T flip-flop and maps ports (via “PORT MAP”) from the top-level entity to the instantiated entity.
2. A look at the synthesized result (via the RTL viewer) shows that the T flip-flop is exactly what is created and nothing more (unlike the previous example where there were 2 flip-flops).
   
   

   Example 2 (RTL viewer)

These two projects illustrate an interesting difference in the way they are created, vis

1. The first project creates an entity in the top-level and directly associates physical pins in the design. The second project is more modular in that block instances (in this case the T flip-flop) are described with their inputs/outputs (and sensible IO names) and stored in libraries. This block is then instantiated and its IO ports are mapped to the actual pins or other blocks in the top-level entity. This is more in line with structured programming in software. I like this method better because reusable blocks can be created with sensible IO names and then mapped to physical pins or other blocks which also use sensible names. In example 1, either the entity names are sensible or the PIN names are but not both. In that I have to either use iKEY0 or oLEDG0 in my entity descriptions or keep my entity names to whatever I like but name the port pins to match the entity port names (I have used the latter in example 1)
2. Another interesting design difference between the two projects is that example 1 is a behavioral description of our design while example 2 is an RTL description (meaning gate level). In the former, the synthesis and optimization phase of the compilation will infer the logic we described. In the latter, the tool has to do less work (although it may further optimize what we described). This implies to me that in behavioral capture we have to know how well certain language constructs will map out or what are good patterns in describing the design so that the synthesis tool will generate the best possible design. This is clearly not the case in example 1 above (I am still learning!).

A final note, that I have alluded to in a previous posting, regards the use of schematic capture. ASAIK the Altera Quartus II design philosophy is to capture all low-level modules in some HDL and then (after converting all these modules into schematic blocks) use schematic capture to tie all these in in the top-level entity.

My First Project in VHDL — Example 1.
My First Project in VHDL — Example 2.

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