We need a basic user interface component to display current settings, such as the current frequency of a frequency generator, say. To this end I will use the seven segment display (SSD) present on the DE2-70. Here I present two designs. One is a straight up look-up table and the other uses a minimized logic function (minimized via Karnaugh Maps) to drive the segments. Note that for the DE2-70 the output logic for driving segments is negative. Thus to turn ON a segment you write a ‘0′ and to turn OFF a segment you write a ‘1′.

Simple Seven Segment Display Driver

The following truth table captures the output for all possible inputs. Note that I plan to display data in hexadecimal and, hence, I am capturing all inputs. The truth table can simplified in the case where one is only displaying digits (0-9) since don’t cares will appear allowing better minimization. Also note that here I am capturing the output as it should be, meaning 0 turns the segment ON and 1 turns the segment OFF. Finally, keep in mind that on the DE2-70 segment a is connected to HEX?_D[0], segment b to HEX?_D[1], etc

The VHDL code for this appears below:

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-- Simple Seven Segment Display Driver for the DE2-70
-- NOTE: Reverse logic: '0' = segment ON; '1' = segment OFF
--       d[0] =>segment_a, d[1] =>segment_b, ... d[6] =>segment_g
-- Author: Hitesh Patel, October 2008
--         blog.nirosoftware.com
--
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
ENTITY SevenSegmentDisplayDriver IS
	PORT ( d : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- input data
	       dp : IN STD_LOGIC; -- decimal point; 1=ON, 0=OFF
	       s : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) -- segment output. MSB is decimal point
	      );
END SevenSegmentDisplayDriver;
 
ARCHITECTURE SevenSegmentDisplayDriver OF SevenSegmentDisplayDriver IS
BEGIN
	WITH d SELECT
		s <= (NOT dp) & "1000000" WHEN "0000",
		     (NOT dp) & "1111001" WHEN "0001",
		     (NOT dp) & "0100100" WHEN "0010",
		     (NOT dp) & "0110000" WHEN "0011",
		     (NOT dp) & "0011001" WHEN "0100",
		     (NOT dp) & "0010010" WHEN "0101",
		     (NOT dp) & "0000010" WHEN "0110",
		     (NOT dp) & "1111000" WHEN "0111",
		     (NOT dp) & "0000000" WHEN "1000",
		     (NOT dp) & "0011000" WHEN "1001",
		     (NOT dp) & "0001000" WHEN "1010",
		     (NOT dp) & "0000011" WHEN "1011",
		     (NOT dp) & "1000110" WHEN "1100",
		     (NOT dp) & "0100001" WHEN "1101",
		     (NOT dp) & "0000110" WHEN "1110",
		     (NOT dp) & "0001110" WHEN "1111",
		     x"FF" WHEN OTHERS; -- all OFF
END SevenSegmentDisplayDriver;

The simulation output shows the results. Note that the decimal point (DP) is OFF.

Following is the project archive for the simple seven segment display driver.

Logic based Seven Segment Display Driver

Here I present the alternative to the above, using logic functions to drive the output. This method requires some understanding of logic minimization techniques of which Karnaugh Maps are probably the most famous. I will not detail how Karnaugh Maps are used as there are (as usual) several very good tutorials online explaining how one can do this. Additionally, there are several interactive online tools to solve logic functions. There is a flash based Karnaugh Map tool, a Java based Karnaugh Map tool and several desktop tools. Logic Friday is a desktop GUI tool that does not use the standard Quine-McCluskey algorithm for logic minimization. It uses a heuristic based minimization technique called the Espresso Algorithm. Finally, if you are into online lectures then you cannot go wrong with the following presented by the MIT equivalent of India, IIT Madras.

Lecture 6 – Karnaugh Maps And Implicants

Lecture 7 – Logic Minimization Using Karnaugh Maps

Here I present the Karnaugh Maps and minimized functions for the truth table (shown above) of the DE2-70 seven segment display. This link presents the truth table and Karnaugh Maps for a Binary Coded Decimal or BCD (ie one that counts from 0 through 9) seven segment display.

Segment A

a = A’B'C’D + A’BC’D’ + ABC’D + AB’CD

Segment B

b = A’BC’D + BCD’ + ABD’ + ACD

Segment C

c = A’B'CD’ + ABD’ + ABC

Segment D

d = A’BC’D’ + B’C'D + BCD + AB’CD’

Segment E

e = A’BC’ + B’C'D + A’D

Segment F

f = A’B'D + A’B'C + A’CD + ABC’D

Segment G

g = A’B'C’ + A’BCD + ABC’D’

The VHDL code for this appears below

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-- Logic based Seven Segment Display Driver for the DE2-70
-- NOTE: Reverse logic: '0' = segment ON; '1' = segment OFF
--       d(0) =>segment_a, d(1) =>segment_b, ... d(6) =>segment_g
-- Author: Hitesh Patel, October 2008
--         blog.nirosoftware.com
--
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
ENTITY SevenSegmentDisplayDriver IS
	PORT ( d : IN STD_LOGIC_VECTOR(3 DOWNTO 0); 	-- input data
	       dp : IN STD_LOGIC; 						-- decimal point; 1=ON, 0=OFF
	       s : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) 	-- segment output. MSB is decimal point
	      );
END SevenSegmentDisplayDriver;
 
ARCHITECTURE SevenSegmentDisplayDriver OF SevenSegmentDisplayDriver IS
BEGIN
	-- segment a
	s(0) <=    ((NOT d(3)) AND (NOT d(2)) AND (NOT d(1)) AND (d(0))) 
			OR ((NOT d(3)) AND (d(2)) AND (NOT d(1)) AND (NOT d(0))) 
			OR ((d(3)) AND (d(2)) AND (NOT d(1)) AND (d(0))) 
			OR ((d(3)) AND (NOT d(2)) AND (d(1)) AND (d(0)));
	-- segment b
	s(1) <=    ((NOT d(3)) AND (d(2)) AND (NOT d(1)) AND (d(0))) 
			OR ((d(2)) AND (d(1)) AND (NOT d(0))) 
			OR ((d(3)) AND (d(2)) AND (NOT d(0))) 
			OR ((d(3)) AND (d(1)) AND (d(0)));
	-- segment c
	s(2) <=    ((NOT d(3)) AND (NOT d(2)) AND (d(1)) AND (NOT d(0))) 
			OR ((d(3)) AND (d(2)) AND (NOT d(0))) 
			OR ((d(3)) AND (d(2)) AND (d(1)));
	-- segment d
	s(3) <=    ((NOT d(3)) AND (d(2)) AND (NOT d(1)) AND (NOT d(0))) 
			OR ((NOT d(2)) AND (NOT d(1)) AND (d(0))) 
			OR ((d(2)) AND (d(1)) AND (d(0))) 
			OR ((d(3)) AND (NOT d(2)) AND (d(1)) AND (NOT d(0)));
	-- segment e
	s(4) <=    ((NOT d(3)) AND (d(2)) AND (NOT d(1))) 
			OR ((NOT d(2)) AND (NOT d(1)) AND (d(0))) 
			OR ((NOT d(3)) AND (d(0))); 
	-- segment f
	s(5) <=    ((NOT d(3)) AND (NOT d(2)) AND (d(0))) 
			OR ((NOT d(3)) AND (NOT d(2)) AND (d(1))) 
			OR ((NOT d(3)) AND (d(1)) AND (d(0))) 
			OR ((d(3)) AND (d(2)) AND (NOT d(1)) AND (d(0)));
	-- segment g
	s(6) <=    ((NOT d(3)) AND (NOT d(2)) AND (NOT d(1))) 
			OR ((NOT d(3)) AND (d(2)) AND (d(1)) AND (d(0))) 
			OR ((d(3)) AND (d(2)) AND (NOT d(1)) AND (NOT d(0))) ;
	s(7) <= NOT dp; -- decimal point	
END SevenSegmentDisplayDriver;

The simulation results appear as follows. The results match the output of the simple SSD driver coded earlier.

Simulation Results for Logic SSD Driver

Following is the Quartus II project archive for the logic version of the seven segment decoder.

At this stage it may be instructive to see what was created using the RTL Viewer and the Technology Map Viewer. The compilation reports for both designs show that 7 logic cells were used. However, if we look at the circuits in the RTL viewer we see that in the former we get MUXs and in the latter it is purely logic gates. Essentially the RTL viewer shows the synthesis results, ie the circuits that are inferred from the design. If we now look at the Technology Map Viewer output, however, we see that almost exactly the same logic is finally realized for both designs. This tool shows the results of mapping the circuit to our technology of choice (in this case the Cyclone II logic).

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