In a couple of previous posts (Counter and Seven Segment Display Decoder) I had put together components designed earlier (a simple counter and a seven segment decoder) for the sake of testing out the components, in particular the seven segment decoder. In that test the top-level entity was constructed entirely in Quartus II via schematic capture. In schematic capture the connection of individual VHDL entities is very easy and the visual nature of the scheme means that one can get a very quick overview of the designer’s intent. However, this hides the details of how the components connect in VHDL and, further, makes the design less portable since the schematic format is proprietary to Altera. I wanted to get a better handle on this and, therefore, decided to implement the same test entirely in VHDL. This, hopefully, gives a better feel for how hierarchical (software equivalent: top-down) design is achieved. I also think that it is important to get into hierarchical or block design early on so that one can start abstracting designs from the beginning.

I will not repeat the intent of the design and refer the reader to this previous post Seven Segment Display Decoder Test (the schematic is clear on what is intended). In summary, count KEY0 presses and display on the seven segment HEX0. This consists of a counter, a seven segment decoder and the top-level entity that combines these other entities. The code below show only the top-level entity. Notice how the counter and the seven segment decoder entities are instantiated via the COMPONENT declaration. Further, note how the signals are mapped via the PORT MAP construct. Also notice how the output of counter is input into the seven segment decoder via a signal.

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-- Seven Segment Display Test. All code is VHDL ONLY.
-- In this project I wanted to attempt the same thing as in in the previous project where
-- where I tested the seven segment display driver. However, in the previous project the 
-- top-level entity was created via schematic capture while here I want to do the same but
-- entirely in VHDL. 
-- Author: Hitesh Patel, November 2008
--         blog.nirosoftware.com
 
LIBRARY ieee;
USE ieee.std_logic_1164.all;
 
ENTITY SSDDriverLogic_TestVHDL IS
    -- NOTE: the following port names are mapped to actual pins. Open the Pin Planner for details.
	PORT( iKEY : IN BIT_VECTOR(3 DOWNTO 0); -- We will clock our design with the iKEY[0]
	      oHEX0_D : OUT STD_LOGIC_VECTOR(6 DOWNTO 0); -- we will output the counter data
												      -- to the seven segment HEX0
	      oHEX0_DP : OUT STD_ULOGIC); 
 
END SSDDriverLogic_TestVHDL;
 
ARCHITECTURE SSDDriverLogic_TestVHDL OF SSDDriverLogic_TestVHDL IS
	--------------------
	COMPONENT counter IS
		GENERIC (NumBits : INTEGER := 4);
		PORT ( clk, clr : IN BIT;
			   c : OUT STD_LOGIC_VECTOR (NumBits-1 DOWNTO 0));
	END COMPONENT counter;
	--------------------
	COMPONENT SevenSegmentDisplayDriver IS
		PORT ( d : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
			   dp : IN STD_LOGIC;
			   s : OUT STD_LOGIC_VECTOR (7 DOWNTO 0));
	END COMPONENT SevenSegmentDisplayDriver;	
	--------------------
	SIGNAL cnt : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
	counter1: counter PORT MAP(clk=>iKEY(0), clr=>'0', c=>cnt);
	ssd: SevenSegmentDisplayDriver PORT MAP(d=>cnt, dp=>'1', s(6 DOWNTO 0)=>oHEX0_D, s(7)=>oHEX0_DP);
END SSDDriverLogic_TestVHDL;

This code brings out all the elements of a typical design and an analogy to software development (especially from the view point of C code) can help better gel the ideas, particularly if you come from that background. In that light note the following:

• The top-level design entity is equivalent to main() in C
• The individual entities are equivalent to function definitions in C
• The COMPONENT declarations in the top-level design entity’s ARCHITECTURE block is equivalent to a function declaration in C.

This analogy can be extended further if we look at creating libraries of common entities. However, I will elaborate on this later since I do not use that in the example presented here.

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