This is a step-by-step guide on my first project on the Avnet Spartan-3A. This will be a very simple project concentrating on the tool flow as opposed to design. To keep things simple we will capture the top level design as a schematic. The design will consist of blinking LED1 (pin D14) at a given rate and controlling LED2 (pin C16) via the CapSense input PUSH_A (pin K3).

The steps to get this going can be summarized as follows:

1. New Project: Start ISE and setup a new project
2. Add sources: Convert all VHDL modules into schematic symbols and then capture the top-level design via schematic capture in ISE.
3. Map I/O: Map inputs and outputs to pins
4. Compile: Compile the design
5. Simulate: Simulate and correct as needed
6. Program Device: Create the bitstream and load into device.

1. New Project

Start the new project wizard by selecting “File—>New Project…” (note that I will be using the latest WebPack version of ISE—version 11). Select a name for the project, a location and optionally give a description. Finally, select the top-Level source type to “Schematic” from the drop-down. See below.

In the next window select device properties. On the Avnet evaluation board we have the 256 pin, Spartan-3A XC3S-400A, speed grade 4 (refer to the Spartan-3A datasheet for details). The following is an excerpt of the package markings

The final settings on the device properties window should be as follows:

Ignore the “Create New Source” window by clicking Next. Do the same for the “Add Existing Sources” window. The last window shows the project summary, click Finish to continue. At this point ISE should look as shown below

2. Add Sources

Create the top-level schematic file by right-clicking on “xc3s400a-4ft256” and selecting “New Source …”. The New Source Wizard will start up. Now select “Schematic” from the selections given, set a file name and hit Next. As follows,

A summary page appears, click Finish to continue. ISE will now automatically open the schematic capture tool as follows:

Now before we continue to schematic capture we need to add a frequency divider module to our design files that will allow us to scale down the FPGA input clock to a smaller value so that it is visible when output to LED1. To do this we will now add a VHDL source to our design. To move away from schematic capture select the “Design” tab from the list of tabs shown in the “Symbols” pane (tabs shown are Design, Files, Libraries and Symbols (currently selected)). After the selection the “Symbols” tab becomes the “Design” tab as follows:

Now as before right-click on “xc3s400a-4ft256” and select “New Source …”, then select “VHDL Module” as the new source and give it a file name, as follows,

Click Next to continue. This will bring up the “Define Module” window of the Wizard. Here set the inputs and outputs of the module as follows (clkIn=IN, divisor=IN(31..0), clkOut=INOUT):

Click Next and then Finish to continue. ISE now shows the basic VHDL module as follows:

We now need to fill in the main code into the VHDL file. Copy and paste the following code into the architecture definition.

PROCESS(clkIn)
    VARIABLE count : STD_LOGIC_VECTOR(30 DOWNTO 0);
    VARIABLE clkOut_t : STD_LOGIC;
BEGIN
    IF(clkIn’EVENT AND (clkIn = ‘1′)) THEN
        count := count + 1;
        IF(count = divisor(31 DOWNTO 1)) THEN
            clkOut <= NOT clkOut;
            count := (OTHERS => ‘0′);
        END IF;
    END IF;
END PROCESS;

The ISE code editor window should look as follows:

Now save the file (CTRL-S) and select “FrequencyDivider” from the file list in the design hierarchy pane. Doing this changes the pane below the Design pane to show the design utilities for the selected file, as follows:

Now double click “Create Schematic Symbol” (highlighted in yellow) to create a schematic symbol of the FrequencyDivider module. Once this process is over double-click on “FirstProject” in the xc3s400a-4ft256 hierarchy (circled in red above). This will now bring up the schematic capture editor. Now the “Design” pane is replaced by the “Symbols” pane. Here all the available symbols are shown including the newly created “FrequencyDivider” symbol. It is possible that this symbol is not shown in the list since the list is not updated. I found that right-clicking in the schematic editor to bring up the context menu has the effect of updating the schematic table, as follows:

Now drag and drop the various modules needed to create our design. This includes the FrequencyDivider, a “constant” under the “General” category and ibuf and obuf under the “IO” category, as follows

Now select the “Add Wire” tool shown in the red circle and connect the ports. Hit ESC to get back to selection mode and double-click on “constant”. This will bring up the “Object Properties” window where the “CValue” needs to be changed to 0×00FFFFFF. Hit OK to continue, as follows:

The Schematic editor should now look as follows:

3. Map IO

We now need to add IO markers or pads. To do this select the “Add—>I/O Marker” menu item (or simply hit CTRL-G) and click on all the IO points in the design. This schematic will now look as follows:

Now assign sensible names to these markers by double-clicking on the IO markers. For example double-clicking the clkIn marker into FrequencyDivider module brings up the following “Object Properties” window. Select the yellow highlighted marks and rename the port. Note the PortPolarity for the port (circled in red). Do the same for the rest. However, for the output port (clkOut) of FrequencyDivider select the PortPolarity from “Bidirectional” to “Output”.

The final schematic is shown below:

Save by hitting CTRL-S or from the menu “File—>Save”. Now select the “Design” tab and select the top-level module FirstProject under the xc3s400a-4ft256 hierarchy. This will bring up various items in the “Processes” pane below the “Design” pane. Now expand the “User Constraints” menu item and double-click on the “I/O Pin Planning (PlanAhead) – PreSynthesis” item, shown highlighted in yellow below:

Since no User Constraints file was created we will be asked to create one, as follows:

Select “Yes” to continue. This will open the “PlanAhead” tool as a separate window.

Now select the various ports under the “I/O Ports” pane (highlighted in yellow) and drag and drop the pins into the pin window (red arrow). The mappings are: clk=>C10, LED1=>D14, LED2=>C16, PUSH_A=>K3. The “I/O Ports” pane should now look as shown below:

Now exit PlanAhead. Now the “Design” tab in ISE should have a file called FirstProject.ucf, right-click on this and select “Open”. This should bring up the “Timing Constraints” pane and editor as shown below:

Now double-click on the editor (highlighted in yellow) to add the clock timing constraints. This will bring up the “Clock Period” window where the clock period for the board can be entered (note that on certain occasions I find that on Vista the tool fails to open with some error pertaining to “TEMP” folder not defined. I simply ignore this error and retry and this usually works OK) . This is 16MHz clock so add 62.5ns in the “Time” textbox, highlighted in yellow, below:

Hit OK to continue. Now save this file by hitting CTRL-S.

4. Compile

Now select the “Design” tab to go back to the design processes. Here select “FirstProject” under the xc3s400a-4ft256 hierarchy and then double-click on “Implement Design” to synthesize and implement the design, as follows (highlighted in yellow):

5. Simulate

I will skip this step for this simple project and take it up in a future posting.

6. Program Device

Now select “Generate Programming File” from the Processes menu to generate the programming file. If you have enabled “WebTalk” then the appropriate “WebTalk” dialog shows up, so respond as needed. Now we will open the Avnet tool AvProg to download the file. Select the highlighted options to connect to the Serial Port, then browse to the Bit File (firstproject.bit) and finally Configure the FPGA, as follows:

The final screenshot of AvProg is shown below. Note the highlighted message indicating that the FPGA programmed successfully.

You will now notice that the LED1 is blinking and that touching the CapSense input PUSH_A causes LED2 to change states.

Notes:

1. I found that the latest edition of ISE WebPack v11 is more stable then v10. I was endlessly fighting the tool when I was using v10 which spuriously kept on changing the UCF file associated with the top-level file—very frustrating.
2. On Vista, I occasionally get a “TEMP” folder does not exist error during various processes (synthesis, UCF creation, etc). I have found that repeating the step normally resolves this problem.
3. When a new file is added to an empty project then the added file is automatically marked as the top-level file. If more files are added later then the top-level file can be reassigned to a new file by simply right-clicking on the file and selecting “Set as Top Module” from the menu. As an example if, in Step 2 above, the VHDL module (FrequencyDivider) was added before the schematic FirstProject then FrequencyDivider would have been marked as the top-level module and subsequent steps would fail. Therefore, we would have to mark the FirstProject file as the top-module before progressing to other steps.

The ISE project archive is included below for download.

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